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Freescale Semiconductor Technical Data
Document number: MC34710 Rev 4, 8/2008
Dual Output DC-DC & Linear Regulator IC
The 34710 is a dual-output power regulator IC integrating switching regulator, linear regulator, supervisory and power supply sequencing circuitry. With a wide operating input voltage range of 13 to 32V, the 34710 is applicable to many commercial and industrial applications using embedded MCUs. A mode-selected 5.0 or 3.3V DC-DC switching regulator is provided for board-level I/O and user circuitry up to 700mA. A linear regulator provides mode-selected core supply voltages of either 3.3V, 2.5V, 1.8V, or 1.5V at currents up to 500mA. The supervisor circuitry ensures that the regulator outputs follow a predetermined power-up and power-down sequence. Features * Efficient 5.0V / 3.3V buck regulator * Low Noise LDO Regulator (mode-selected 3.3V, 2.5V,1.8V, or 1.5V) * On-chip thermal shutdown circuitry * Supervisory functions (Power-ON Reset and Error Reset circuitry) * Sequenced I/O and core voltages * Pb-free packaging designated by suffix code EW
34710
DUAL OUTPUT DC-DC & LINEAR REGULATOR
EW SUFFIX (PB-FREE) 98ASA10627D 32-PIN SOICW
ORDERING INFORMATION
Device MC34710EW/R2 Temperature Range (TA) 0C to 85C Package 32 SOICW-EP
VI/O
13 V to 32 V
34710
B+
VB CP2 CP1 MODE0 MODE1 MODE2 RST LINB+ VCORE GND VCORE CT VSWITCH VFB VI/O
MCU
Figure 1. 34710 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
B+
200 kHz Oscillator
Charge Pump
CP1 CP2 VB
Supervisory and Temperature Shutdown
RST CT
Bandgap VI/O Switching Regulator VCORE Linear Regulator
VFB VSWITCH
MODE0
MODE1 MODE2 LINB+
VCORE
GND
Figure 2. 34710 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
RST MODE0 MODE1 MODE2 N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CT CP1 CP2 VB B+ VSWITCH VFB LINB+ N/C VCORE N/C N/C N/C N/C N/C N/C
Figure 3. 34710 Pin Connections Table 1. 34710 Pin Definitions
Pin Number 1 2 3 4 5 - 12, 14 -22, 24 13 23 25 26 Pin Name
RST
Pin Function Reset Input
Formal Name Reset Mode Control
Definition Reset is an open drain output only. These input pins control VFB and VCORE output voltages.
Mode0 Mode1 Mode2 NC GND VCORE LINB+ VFB
NC Ground Output Input Input
No Connects Ground Core Voltage Regulator Output Core Voltage Regulator Input VI/O Switching Regulator Feedback VI/O Switching Regulator Switch Output Power Supply Input Boost Voltage CP Capacitor Positive CP Capacitor Negative Reset Delay Capacitor
No internal connection to this pin. Ground. Core regulator output voltage. Core regulator input voltage. Feedback pin for VI/O switching regulator and internal logic supply.
27
VSWITCH
Output
VI/O switching regulator switching output.
28 29 30 31 32
B+ VB CP2 CP1 CT
Input Output Passive Component Passive Component Passive Component
Regulator input voltage. Boost voltage storage node. Charge pump capacitor connection 2. Charge pump capacitor connection 1. Reset delay adjustment capacitor.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating ELECTRICAL RATINGS Input Power Supply Voltage IB+ = 0.0A Peak Package Reflow Temperature During Reflow , Power Dissipation(3) ESD Standoff Voltage Non-Operating, Unbiased, Human Body Model(4) Thermal Resistance Junction-to-Ambient(5) Junction-to-Ambient(3) Junction-to-Exposed-Pad THERMAL RATINGS Operating Ambient Temperature Operating Junction Temperature Input Power Supply Voltage IB+ = 0.0A to 3.0A Quiescent Bias Current from B+(6) VB+ = 13 to 32V VI /O SWITCHING REGULATOR(7) Maximum Output Voltage Startup Overshoot (COUT = 330F) Mode0 = 0 Mode0 = Open Maximum Output Current TA = 0C to 105C IVI/O 700 VI / O(STARTUP) 5.4 3.6 mA V IB+(Q) 7.5 TA TJ VB+ 13 to 32 mA 0 to 85 0 to 105 C C V RJA RJA RJC 45 25 2.0 VESD1 2000 C/W
(1) (2)
Symbol
Max
Unit
VB+ -0.3 to 36 TPPRT PD Note 2 3.0
V
C W V
Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 2. 3. 4. 5. 6. 7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. With 2.0 in2 of copper heatsink. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100pF, RZAP = 1500). With no additional heatsinking. Maximum quiescent power dissipation is 0.25W. 13V VB+ 32V and - 20C TJ 145C, unless otherwise noted.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating VCORE LINEAR REGULATOR
(8)
Symbol
Max
Unit
Maximum Output Voltage Startup Overshoot (COUT = 10F) (9) Mode2=Low, Mode1=Low, Mode0=Low Mode2=Open, Mode1=Low, Mode0=Don't Care Mode2=Low, Mode1=Open, Mode0=Don't Care Mode2=Open, Mode1=Open, Mode0=Don't Care Maximum Output Current TJ = 0C to 105C, VLINB+ VCORE (NOM) + 0.8V
(10)
VCORE (STARTUP) 3.6 2.7 2.0 1.65 IVCORE 500
V
mA
Notes 8. 13V VB+ 32V and - 20C TJ 145C, unless otherwise noted. 9. 10. Refer to Table 5, page 9. Pulse testing with low duty cycle used.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75V VIO 5.25V, 13V VB+ 32V, and 0C TJ 105C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SWITCHING REGULATOR (VI/O, MODE0) Logic Supply Voltage (IVI/O = 25 to 700mA) Mode0 = 0 Mode0 = Open (floating) Output On Resistance VB+ = 13 to 32V Soft Start Threshold Voltage Mode0 = any Current Limit Threshold (TJ = 25C to 100C) Normal Operation Soft Start, VI / O 2.5V Minimum Voltage Allowable on VSWITCH Pin TJ = 25C to 100C LINEAR REGULATOR (VCORE, MODE 1, 2, 3, 4) Supply Voltage (IVCORE = 5.0mA)(11) Mode2=Low, Mode1=Don't Care, Mode0=Low Mode2=Low, Mode1=Don't Care, Mode0=Open Mode2=Open, Mode1=Don't Care, Mode0=Low Mode2=Open, Mode1=Don't Care, Mode0=Open Supply Voltage (IVCORE = 500mA)(11) Mode2=Low, Mode1=Don't Care, Mode0=Low Mode2=Low, Mode1=Don't Care, Mode0=Open Mode2=Open, Mode1=Don't Care, Mode0=Low Mode2=Open, Mode1=Don't Care, Mode0=Open VCORE Dropout Voltage VCORE = VCORE (NOM), IVCORE = 0.5A Normal Current Limit Threshold TJ = 25C to 100C, VLINB+ = VCORE (NOM) + 1.0V Notes 11. Refer to Table 5, page 9. ILIMIT 600 800 1000 IVCORE(DROPOUT) - 0.5 0.8 mA VCORE (NOM) 3.0 2.2 1.55 1.33 - - - - 3.4 2.6 1.9 1.53 V VCORE (NOM) 3.15 2.45 1.7 1.425 3.3 2.5 1.8 1.5 3.45 2.75 2.05 1.575 V V ILIMIT (OP) ILIMIT (SOFT) VVSWITCH (MIN) -0.5 - - 1.9 1.0 2.4 - 2.9 1.9 V VI / O(SOFT) - 2.5 3.1 A RDS(ON) 0.5 1.0 2.0 V VI / O 4.8 3.15 5.0 3.25 5.2 3.45 V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75V VIO 5.25V, 13V VB+ 32V, and 0C TJ 105C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic MODE PINS OPERATING VOLTAGES Mode Control Pins Low Voltage VIL(Moden) - Mode Control Pins High Voltage VIH (Moden) 2.6 Mode Control Pins Voltage with Input Floating VB+ = 13 to 14V SUPERVISOR CIRCUITRY (RST, VCORE) Minimum Function VB+ for Charge Pump and Oscillator Running Minimum VB+ for RST Assertion, VB+ Rising
RST Low Voltage
Symbol
Min
Typ
Max
Unit
V - 0.825 V - - V 7.0 8.0 13
VMode(FLOAT)
VB+ (MIN) VB+(ASSERT) VOL
- -
- 1.9
9.0 2.2
V V V
VB+ = 2.0V, IRST 5.0mA
RST VI / O Threshold
-
0.25
0.4 V
VI / O Rising VI / O Falling
RST Hysteresis for VI / O RST VCORE Threshold
VI / OT+ VI / OTVHYSVI/O
- VI/O (NOM)
- - -
VI/O(NOM)
- 50mV
- 100 mV V
- 300mV
10
VCORE Rising VCORE Falling
RST Hysteresis for VCORE
VCORET+ VCORETVHYS CORE
- VCORE (NOM)
- -
VCORE (NOM)
- 30mV
- mV
- 300mV
10
VB+ = 13 to 32V VCORE - VI / O for VCORE Shutdown VB+ = 13 to 32V Thermal Shutdown Temperature TJ Rising Over-temperature Hysteresis VB CHARGE PUMP Boost Voltage(12) VB+ = 12 V, Ivb = 0.5 mA VB+ = 32 V, Ivb = 0.5 mA Notes 12. Bulk capacitor ESR 10 milliohms TJ (HYSTERESIS) TJ (TSD) VCORE (SHUTDOWN)
50
100 V
0.5
-
0.9 C
- -
- 20
170 - C
V
VB VB
VB+ 8 VB+ 10
VB+ 9 VB+ 12
VB+ 10 VB+ 14
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75V VIO 5.25V, 13V VB+ 32V, and 0C TJ 105C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted
Characteristic VI /O SWITCHING REGULATOR Duty Cycle Switching Rise and Fall Time Load Resistance = 100, VB+ = 30V SUPERVISOR CIRCUITRY (RST)
RST Delay
Symbol
Min
Typ
Max
Unit
D t R , tF
45
49
55
% ns
20
35
50
t DELAY 40 t FILTER 2.0 tF - 25 75 4.0 8.0 60 80
ms
Cdelay = 0.1F
RST Filter Time
s
VB+ = 9.0V
RST Fall Time
ns
CL = 100pF, RPULLUP = 4.7k, 90% to 10% C Delay Charge Current Threshold Voltage INTERNAL OSCILLATOR Charge Pump and VI / O Switching Regulator Operating Frequency VB+ = 12 to 32V f OP ICDLY VTHCD
2.0 1.7
3.5 2.0
5.0 2.2
A V
kHz 140 170 260
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION VI /O Switching Regulator
The VI /O switching regulator output voltage is determined by the Mode digital input pins. The 34710's Mode pins select the output voltage. For example, if Mode2, Mode1, and Mode0 are set to 0, 0, 0 (respectively) then VI /O will be set to 5.0V; if Mode2, Mode1, and Mode0 are all left floating (i.e., Open, Open, and Open), then the voltage for VI /O will be set to 3.3V. Table 5 provides the truth table for setting the various combination of regulator outputs via the Mode pins. The topology of the regulator is a hysteretic buck regulator operating from the internal ~200kHz oscillator. voltage + 0.8V. (I.e., 0.8V is the LDO regulator drop out voltage.) The Mode pins select the output voltage as depicted in Table 5. Table 5. VI /O and VCORE Regulator Output Voltage Selection
Mode2 0 0 0 0 Open Open Open Open Mode1 0 0 Open Mode0 0 Open 0 Open 0 Open 0 Open VI /O (V) 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 VCORE (V) 3.3 2.5 1.8 1.8 2.5 2.5 1.5 1.5
VCORE Linear Regulator
The VCORE linear LDO (low drop-out) regulator can produce either a +3.3V, 2.5V, 1.8V, or 1.5V output voltage at currents up to 500mA. The input to the VCORE regulator is a pin that may be connected to the VI /O regulator output or to an external power supply. Note, the minimum input voltage level must be equal to or greater than the selected VCORE
Open
0 0 Open Open
Open indicates pin is not connected externally (i.e. floating).
FUNCTIONAL PIN DESCRIPTION POWER SUPPLY INPUT (B+)
Main supply voltage for the VI/O Switching Regulator and general chip bias circuitry. fault conditions. This pin has no input function and requires an external pull-up resistor. The RST pin is an open drain output driver to prevent oscillations during the transition. It is recommended to connect a 0.1uF capacitor between the CT pin and RST pin. Note: error conditions must be present for a minimum time, tFILTER, before the 34710 responds to them. Once all error conditions have been cleared, RST is held low for an additional time of tDELAY.
CORE VOLTAGE REGULATOR INPUT (LIN B+)
Supply voltage for the VCORE Regulator. May be provided by the VI/O regulator output or from an independent supply.
MODE CONTROL (MODE 0,1,2)
Mode select pins to select the VI/O and VCORE output voltages per table 2. Pull to ground for low state, float for high state.
RESET DELAY CAPACITOR (CT)
This pin is the external delay. It is used with a capacitor to ground to delay RST turn-on time and to RST to prevent RST oscillations during chip power-on.
SWITCHING CAPACITORS 1 AND 2 (CP1/CP2)
Pins for the Charge Pump capacitor.
VI/O SWITCHING REGULATOR FEEDBACK (VFB) BOOST VOLTAGE (VB)
The Boost Voltage is an output pin used for the charge pump boost voltage and is a connection point for the Charge Pump bulk capacitor.It provides a gate drive for the VI/O Switch FET. This pin is the feedback input for the VI/O Switching Regulator and the output of the regulator application.
VI/O SWITCHING REGULATOR OUTPUT (VSWITCH)
This pin is the Switching output for the VI/O Buck Regulator. It has internal high side FET.
RESET (RST)
Reset is an output pin for supervisory functions. This pin is in high state during normal operation and low state during
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
SUPERVISORY FUNCTIONS
Supervisory Circuitry The supervisory circuitry provides control of the RST line, an open drain signal, based on system operating conditions monitored by the 34710. VI /O, VCORE, VB+, and thermal shutdown (TSD) detectors in various parts of the chip are monitored for error conditions. VI /O, VCORE, VB+, and thermal shutdown have both positive and negative-going thresholds for triggering the reset function. The supervisor circuitry also ensures that the regulator outputs follow a predetermined power-up and power-down sequence. Specifically, the sequencing ensures that VI /O is never less than 0.9V below VCORE. This means that VCORE VI /O will be clamped at 0.5V, and that the VCORE regulator
operation will be suppressed during startup and shutdown to ensure that VCORE - VI /O = 0.9V. VB Charge Pump The high side MOSFET in the switching regulator (buck converter) requires a gate drive supply voltage that is biased higher than the B+ voltage, and this boosted voltage is provided by the internal charge pump and stored in a capacitor between the VB pin and the B+ pin. The charge pump operates directly from the B+ supply, and uses an internal oscillator operating at 200kHz. Internal Oscillator The internal oscillator provides a 200kHz square wave signal for charge pump operation and for the buck converter.
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
B+ 13- 32V
C1 330F
R1 1K SW1 1 RST 2 MODE0 3 MODE1 4 MODE2
C1 0.1mF CT 32 31 CHARGE CP1 30 PUMP CP2 VB 29 28 B+ BUCK 27 REG VSW 26 VFB 25 LINB 24 LDO 23 VCORE C5 0.1F C6 10F L1 100H
SUPERVISORY & SHUTDOWN
RSERIES 1.8
D1 MBRS130LT3
C8 330F
13
GND
MC34710
1 2
V I/O VCORE
Figure 4. Typical Application Diagram The MC34710 provides both a buck converter and an LDO regulator in one IC. Figure 4 above shows a typical application schematic for the MC34710. L1 is the buck converter's inductor. The buck inductor is a key component and must not only present the required reactance, but do so at a DC resistance of less than 20 milliohms in order to preserve the converter's efficiency. Also important to the converter's efficiency is the utilization of a low VF Schottky diode for D1. Note that a 0.1uF capacitor is connected between CT and the reset pins; this prevents any possibility of oscillations occurring on the reset line during transitions by allowing the CT pin to discharge to ground potential via the RST pin, and then charge when RST returns to a logic high. The capacitor between the CP1 and CP2 pins is the charge pump's "bucket capacitor", and sequentially charges and discharges to pump up the reservoir capacitor connected to the VB pin. Note that the reservoir capacitor's cathode is connected to B+ rather than ground. Also note that the charge pump is intended only to provide gate-drive potential for the buck regulator's internal power MOSFET, and therefore connecting external loads to the VB pin is not recommended. The IC's internal VCORE LDO regulator can provide up to 500mA of current as long as the operating junction temperature is maintained below 105 degrees C. The heatgenerating power dissipation of the LDO is primarily a function of the Volt x Amp product across the LINB+ and VCORE pins. Therefore, if the LINB+ voltage is >> than the selected VCORE voltage + 0.8V, it is recommended to use a power resistor in series with the LINB+ input to drop the voltage and dissipate the heat externally from the IC. For example, if the output of the buck regulator (V I/O on the schematic) is used as the input to LINB+, and the mode switches are set such that V I/O = 5V and VCORE = 3.3 , then a series resistance of 1.8 ohms at the LINB+ pin would provide an external voltage drop at 500mA while still leaving the minimum required headroom of 0.8V. Conversely, if the mode switches are set such that V I/O = 3.3V and VCORE = 2.5V, then no series resistance would be required, even at the maximum output current of 500mA. Designing a power supply circuit with the MC34710, like all DC-DC converter ICs, requires special attention not only to component selection, but also to component placement (i.e., printed circuit board layout). The MC34710 has a nominal switching frequency of 200kHz, and therefore pcb traces between the buck converter discrete component pins and the IC should be kept as short and wide as possible to keep the parasitic inductance low. Likewise, keeping these pcb traces
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TYPICAL APPLICATIONS
short and wide helps prevent the converter's high di/dt switching transients from causing EMI/RFI.
possible. The square vias in the plane are located to provide an immediate path to ground from the top copper circuitry.
Figure 5. Typical PCB Layout Figure 5 shows a typical layout for the pcb traces connecting the IC's switching pin (VSWITCH) and the power inductor, rectifier, and filter components. Also, it is recommended to design the component layout so that the switching currents can be immediately sunk into a broad full-plane ground that provides terminations physically right at the corresponding component leads. This helps prevent switching noise from propagating into other sections of the circuitry.
Figure 7. Top Copper Layout Figure 7 shows the corresponding top copper circuit area with the component placement. Again, the ground plane and the vias have been highlighted so the reader may note the proximity of these current sink pathways to the key converter components. It is also important to keep the power planes of the switching converter's output spread as broad as possible beneath the passive components, as this helps reduce EMI/RFI and the potential for coupling noise transients into adjacent circuitry.
Figure 6. Bottom Copper Layout Figure 6 illustrates a pcb typical bottom copper layout for the area underneath a buck converter populated on the top of the same section of pcb. The ground plane is highlighted so the reader may note how the ground plane has been kept as broad and wide as
Figure 8. Output Plane of Buck Converter Figure 8 shows the output plane of the buck converter highlighted.
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TYPICAL APPLICATIONS
This layout provides the lowest possible impedance as well as lowest possible dc resistance for the power routing. Note that the power path and its return should be placed, if possible, on top of each other on different layers or opposite sides of the pcb. Small ceramic capacitors are placed in parallel with the Aluminum electrolytics so that the overall bulk filtering presents a low ESL to the high di/dt switching currents. Alternatively, special low ESL/ESR switching-grade electrolytics may be used.
An additional feature of the MC34710 is the 32 SOICW-EP exposed pad package. The package allows heat to be conducted from the die down through the exposed metal pad underneath the package and into the copper of the pcb. In order to best take advantage of this feature, a grid array of thru-hole vias should be placed in the area corresponding to the exposed pad, and these vias then should then connect to a large ground plane of copper to dissipate the heat into the ambient environment. An example of these vias can be seen in the previous figures of a typical pcb layout.
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD 98ASA10627D ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD 98ASA10627D ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD 98ASA10627D ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 2.0
DATE 8/2008
DESCRIPTION OF CHANGES * * * * * * * * * * * * Converted to Freescale format Updated Maximum Ratings, Static and Dynamic Characteristics tables. Updated packaging drawing Changed pin VI/O_OUT to VFB Implemented Revision History page Updated format from Preliminary to Advance Information. Format and style corrections to match standard template. Update the Freescale format and style Changed the reflow parameter name to Peak Package Reflow Temperature During Reflow(1), (2) Removed PC33710EW/R2 from the ordering information. Changed Advance status to Final Update the package drawing to Rev B.
3.0 4.0
3/2006 8/2008
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MC34710 Rev 4 8/2008

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